1. Field of the Invention
This invention relates generally to data processing systems and, more particularly, to data processing systems capable of performing scalar and vector operations
2. Description of the Related Art
In order to increase the performance of certain types of repetitious operations, the technique of vector data processing operations has been developed. For example, a vector add operation can be used to add the corresponding elements of two data arrays (generally referred to as vector arrays) together and store the resultant sums in a third data array. This operand processing procedure can be contrasted with scalar instructions implementing the same computation which would require repeated execution of a loop routine. Vector processing has the advantage of specifying, in a single instruction, the processing of large amounts of data without the need to issue multiple instructions or perform loop iteration control. In addition, since the same operation is being applied to each set of operands, pipelining techniques can be efficiently employed to increase performance. In general, two models of vector array processing have emerged, the register based model and the memory based model.
In the resister based model, sets of operands are transferred (loaded) from main memory and stored in special registers referred to as vector registers. Each vector register can store a multiplicity of operands, each set of operands having a predetermined length. When one or more vector registers have the required operands stored therein, then all the operands stored in the vector register are processed by a common arithmetic operation and the operands resulting from the processing operation are stored in target vector register locations. Because the same operation is performed on all the operands of the vector register, only one instruction need be issued to the processing execution unit to manipulate a multiplicity of operands. After all the requisite operations are performed on the set of operands, the operands are returned to (or stored in) the main memory unit.
In the memory based model, the operands are transferred directly from the main memory unit to the execution unit and the resulting operands are returned directly to the main memory unit.
When intermediate results are present in a computation (which is often the case), the memory-based model must store the intermediate results in memory and fetch them again for each successive use. When a vector memory fetch operation is started, a certain amount of time is required before the first operand arrives from memory. Also, as ports to the main memory unit are expensive and hence limited in number, the presence of vector memory operations in progress may further delay the arrival of the first operand from memory.
The register-based model, however, does not incur the penalty of repeatedly storing and fetching intermediate results because they are available without memory latency when they are present in a vector register. Thus, the register-based model results in higher performance, in general, unless the vectors are of sufficient length that the long start-up period resulting from the memory latency is negligible compared to the length of the vector array. Because the register-based model is effective for short as well as long vectors, it has become more widely used than the memory-based model.
One difficulty with prior art register-based models is that the elements of vector operands and scalar operands are stored in different register sets and different instructions are needed to operate on the different register sets. Furthermore, scalar operations can not be applied to a single operand (i.e., element) in a vector register. Instead all the operands in the vector register must be stored into the main memory unit from the vector register and the desired single operand fetched into a scalar register. If further vector processing involving this single operand is required, it must be stored and all the elements of the vector operand must be fetched into the vector register. As a practical matter, many computations involve mixed scalar and vector operations on operands, so the distinction between elements in vector operands and scalar operands requires costly memory operations.
A need has therefore been felt for an operand processing technique which eliminates the distinction between operands in vector registers and operands in scalar registers, and the attendant limitations on the operations thereon. This technique further reduces overhead of storing and fetching operands between computations.